Circuit Design Environment and Layout Planning

Circuit design in deep sub-micron technologies requires that designers deal with numerous data, constraints, analysis, synthesis, and optimization tools. Although synthesis tools are widely used at Intel, new circuit technologies are evolving and are often not well supported by existing synthesis tools. Deep sub-micron technology requires that the impact of physical design be considered early in the circuit design phase to prevent costly circuit, layout, and sometimes, logic re-design. A common source of these re-designs is inaccurate assumptions about the layout aspects of the target design. Thus, early layout planning and accurate parasitics estimation must be done by circuit designers. Intel’s FUB Circuit Design Environment (FCDE) is an integrated, interactive, and incremental circuit design environment that incorporates multiple tools, data, constraints, and analysis tools. FCDE integrates all circuit design tools including circuit simulation, layout planning, parasitics estimation, timing analysis, circuit optimizers. Circuit design tools exchange data via a common data model (Unified Core Model). FCDE tools expose their functionality to each other by standard tool drivers that allow integration of in-house design tools as well as vendor design tools. FCDE was designed and implemented on the Windows NT ∗ operating system, and uses native Windows* technologies such as Microsoft∗ Component Object Model (COM), Visual Basic∗ and Visual Basic for Applications∗ (VBA). This paper describes Intel’s circuit design environment and its components, with special emphasis on the layout planner, and its role in circuit design flows. Results from a recent microprocessor design project support the need for layout planning by showing that the amount of re-design and re-work required for blocks is reduced when early layout planning is carried out. Introduction Traditional custom integrated circuit design methodology can be depicted as a waterfall model, where a stage (e.g., logic design) is completed and the results passed on to the next stage (e.g., circuit design). Results at each stage are evaluated without any consideration of their effect on later stages. For example, interconnect loading is assumed during circuit design for technology mapping. This assumption is likely to be invalidated during the layout design phase. Thus, the final layout is analyzed to verify functionality. If there are problems, then the layout is re-designed in an attempt to correct them. If the redesigned layout fails to correct the problems, then a re-design at one of the previous stages in the flow is attempted. This flow (shown in Figure 1) is very time consuming and expensive due to the follow-